The invention relates to integrated circuit memory devices and fabrication of the same. More specifically, the invention relates to electronically erasable programmable read only memory (EEPROM) cells.
The semiconductor community faces increasingly difficult challenges as it moves into production of continually smaller semiconductor devices. Memory cell designs for typical semiconductor memory devices must be made more durable, smaller (i.e., scalable), cost effective to manufacture, faster in reading and writing and capable of operating at lower voltages to enable manufacturers to compete in the semiconductor industry. Given the considerable commercial importance placed on small memory cell size, further miniaturization of the memory cell is desirable.
A memory array comprises a plurality of data carrying lines, a plurality of word lines, and a plurality of memory cells. A typical memory cell comprises a select transistor coupled to an EEPROM transistor. The EEPROM transistor has a floating gate and also a drain coupled to an associated one of the data carrying lines. The select transistor has a source coupled to a data carrying line adjacent the associated data carrying line. The gate of the select transistor and the EEPROM transistor gates are commonly coupled to an associated one of the word lines.
For example, as shown in FIG. 1, a memory cell 10 may comprise an n-type source 16 and drain 20 disposed in a p-type semiconductor substrate 18. A control gate contact 12 is connected to a heavily doped n+ region of the substrate at the source 16. A coupling capacitor 24, typically formed of a thermally grown silicon dioxide layer, overlies the heavily doped n+ region of the substrate 18. The coupling capacitor 24 is coupled to a floating gate 28. The floating gate 28 extends from the coupling capacitor 24 over an isolation area 32 in the substrate 18 to a tunneling oxide layer 36. Tunneling oxide layer 36 overlies the drain 20. The control gate contact 12 connected to the coupling capacitor 24 is shared by four or more adjacent memory cells.
Such a memory cell 10 as shown in FIG. 1 would be only one of an array of memory cells in an EEPROM device. Although such a memory cell 10 has proven useful in EEPROM memory arrays, given the considerable commercial importance placed on small memory cell size, further miniaturization of the memory cell and EEPROM array size is desirable.
In U.S. Pat. No. 4,713,677, an EEPROM memory cell includes a trench capacitor in effort to minimize memory cell size as well as to reduce the operating voltage necessary for programming the device. The memory cell disclosed in U.S. Pat. No. 4,713,677 is configured such that a control gate, a dielectric layer forming the coupling capacitor and a floating gate are all formed in a trench. In addition, however, each of these components of the memory cell also extends outside the trench and over the length of the memory cell. Thus, although coupling capacitance does occur in the trench it also occurs over the entire cell that unnecessarily increases the process complexity. In addition, such a coupling capacitor as disclosed in U.S. Pat. No. 4,713,677, requires two physically separate polysilicon layers to form the capacitor cell again adding to the process complexity. Lastly, with such a structure, the memory cell size is still larger than desirable.
The disclosed EEPROM memory cell and array achieves a dramatically smaller memory cell for an EEPROM device. Further, one or more embodiments of the present memory cell achieves a smaller memory cell utilizing known shallow trench isolation (STI) fabrication techniques to form a trench capacitor. As is known to those persons skilled in the art, there is a significant amount of time and cost associated with performing a STI process. In addition, expensive equipment is utilized to carry out STI processing. Because the trench coupling capacitor of the memory cell disclosed herein may be formed utilizing shallow trench isolation, the capacitor may be formed using equipment typically present in memory chip fabrication plants. Further, any xe2x80x9cfine-tuningxe2x80x9d and prior expenditures associated with the STI process is utilized to form the trench coupling capacitors of the memory cell, saving additional time and expense. Also, a control gate-coupling ratio of one or more of the disclosed memory cell embodiments may be increased with the reduced memory cell size.
An embodiment of the memory cell for an EEPROM device may comprise a trench coupling capacitor wherein a coupling oxide is formed only in the trench (i.e., all coupling occurs in the trench). In addition, a portion of a floating gate of the memory cell is formed in the trench to function as a conductive portion of the capacitor as well as a floating gate. More specifically, an embodiment of the EEPROM device may comprise a substrate having a doped region formed therein. A first trench is formed in the doped region of the substrate. A coupling capacitor formed in the first trench, comprises a bottom conductive portion formed by the doped region of the substrate, a coupling oxide layer lining the trench and a floating gate first portion covering the coupling oxide layer. A floating gate second portion is electrically connected to the first portion. A control gate is connected to the doped region of the substrate and a thin tunnel dielectric physically separates the floating gate second portion from the coupling oxide layer and from the doped region of the substrate.
The specifically described fabrication method and device embodiments are set forth for illustration. It is understood, however, that the invention is not limited to those specifically described embodiments.